Schottky Diode Reverse Recovery Time Characteristics
Technical Background of Schottky Diode Reverse Recovery Time
Schottky barrier diodes (SBDs) are core high-frequency rectification components featuring zero minority carrier storage, ultra-fast switching speed, and low forward voltage drop, widely used in high-frequency switch-mode power supplies (SMPS), RF front-end circuits, automotive electronic DC-DC converters, and renewable energy grid-connected inverters. Reverse recovery time (trr) is a critical performance parameter of Schottky diodes, defined as the time required for the reverse recovery current to decay from its peak value to 10% of the peak after the diode switches from forward conduction to reverse cutoff under specified test conditions. Unlike PN-junction rectifier diodes, Schottky diodes rely on majority carrier conduction, resulting in an extremely short trr (typically in the range of 1-50ns), which is the key to their adaptation to high-frequency (≥1MHz) working scenarios. In a 2MHz SMPS circuit, a Schottky diode with trr = 10ns can reduce switching losses by 60% compared to a fast recovery diode with trr = 100ns, significantly improving circuit conversion efficiency. The reverse recovery time of Schottky diodes is mainly determined by the metal-semiconductor barrier height, semiconductor substrate doping concentration, and device junction area design. Mainstream commercial Schottky diodes are categorized into three types: silicon-based SBDs, silicon carbide (SiC)-based SBDs, and gallium nitride (GaN)-based SBDs, with distinct differences in their reverse recovery time characteristics and frequency adaptation capabilities. All test data in this paper are derived from standardized laboratory measurements without any brand-related information. The baseline test environment is 25℃ and 50%RH, and the test equipment includes a 1GHz bandwidth digital oscilloscope, high-speed pulse signal generator, high-precision DC power supply, and high-low temperature test chamber, ensuring the objectivity and industry universality of the test data.
Test Methods for Schottky Diode Reverse Recovery Time
This test adopts the standard dynamic characteristic test method for high-frequency semiconductor diodes, accurately measuring the reverse recovery time of Schottky diodes while eliminating interference from circuit parasitic inductance, stray capacitance, and electromagnetic radiation, fully complying with the IEC 60747-5-1 international standard for Schottky diode electrical performance testing. The specific test process is as follows: First, select three groups of Schottky diode samples with the same package size (SMA, 4.9mm×2.8mm), rated forward current (IF = 5A), and rated reverse voltage (VR = 40V), differing only in the semiconductor substrate material: silicon-based SBD, SiC-based SBD, and GaN-based SBD, with 30 samples in each group to avoid process deviations of individual samples. Second, build the industry-standard double-pulse test circuit: connect the diode in series with an energy storage inductor and a high-speed MOSFET switch, apply a forward bias voltage to conduct the diode and establish a steady forward current (set to 5A), then switch the MOSFET to apply a reverse bias voltage (set to 40V) to trigger the diode's turn-off process. Third, use an oscilloscope to capture the reverse recovery current (Irr) and voltage (VR) waveforms in real time, measure the time interval from the moment the forward current drops to zero to the moment the reverse recovery current decays to 10% of its peak value, which is defined as the reverse recovery time (trr). Fourth, complete supplementary multi-dimensional tests, including temperature characteristic tests (-40℃, 25℃, 85℃, 125℃), forward current dependence tests (1A, 3A, 5A, 8A), and 1000-hour high-temperature aging tests (85℃, continuous forward conduction with 5A current), covering all core working conditions of Schottky diode applications.
In this test, each test condition is repeated 20 times for each sample, and the arithmetic average is taken after removing the maximum and minimum values, with the overall test error of reverse recovery time controlled within ±1ns. During the test, the test circuit's parasitic inductance is calibrated to ≤5nH using a precision impedance analyzer to avoid waveform distortion caused by inductive voltage spikes. All test links are free of brand and manufacturer-related information, and the data have universal reference value.
Schottky Diode Reverse Recovery Time Characteristic Data
1. Room temperature baseline reverse recovery time data: At 25℃, with a forward current of 5A and a reverse voltage of 40V, the reverse recovery time of the silicon-based SBD is 35ns, with a reverse recovery current peak (Irrm) of 3.2A; the SiC-based SBD has a trr of 8ns and an Irrm of 1.5A; the GaN-based SBD has an ultra-short trr of 2ns and an Irrm of 0.8A. The core reason for the significant differences lies in the conduction mechanism: silicon-based SBDs still have a small amount of minority carrier injection at high currents, leading to a relatively long trr; SiC and GaN are wide bandgap semiconductors, with negligible minority carrier storage effects, thus achieving ultra-fast switching. Under the same device type, when the forward current increases from 1A to 8A, the trr of the silicon-based SBD increases from 12ns to 50ns, with a variation rate of 316.7%; the trr of the GaN-based SBD increases from 1ns to 3ns, with a variation rate of only 200%, showing stronger current stability. This is because the high doping concentration of wide bandgap semiconductor substrates suppresses minority carrier accumulation even at high currents.
2. Temperature-dependent reverse recovery time data: The reverse recovery time of Schottky diodes exhibits a weak negative temperature coefficient characteristic, meaning that trr decreases slightly with increasing temperature, which is a key advantage distinguishing them from PN-junction diodes. At a forward current of 5A and a reverse voltage of 40V, the trr of the silicon-based SBD is 42ns at -40℃, 35ns at 25℃, and 30ns at 125℃, with a temperature coefficient of -0.1ns/℃; the SiC-based SBD has a trr of 10ns at -40℃, 8ns at 25℃, and 7ns at 125℃, with a temperature coefficient of -0.025ns/℃; the GaN-based SBD's trr changes only from 2.2ns at -40℃ to 1.8ns at 125℃, showing almost no temperature dependence. The core reason is that high temperatures increase the mobility of majority carriers, accelerating the dissipation of reverse recovery current, while the minority carrier storage effect of silicon-based SBDs is further suppressed at high temperatures, leading to a more obvious reduction in trr.
3. Reverse voltage dependence reverse recovery time data: The reverse recovery time of Schottky diodes has a weak positive correlation with the reverse bias voltage. At 25℃ and a forward current of 5A, when the reverse voltage increases from 20V to 60V, the trr of the silicon-based SBD increases from 30ns to 40ns, with a variation rate of 33.3%; the trr of the SiC-based SBD increases from 7ns to 9ns, with a variation rate of 28.6%. This is because higher reverse voltage strengthens the electric field in the depletion region, accelerating the drift of majority carriers, but at the same time increases the peak value of the reverse recovery current, leading to a slight extension of the current decay time. However, the influence of reverse voltage on trr is far smaller than that of forward current and temperature, which is a secondary influencing factor.
4. Long-term high-temperature aging reverse recovery time data: After 1000 hours of high-temperature aging testing at 85℃ under continuous forward conduction with 5A current, the trr of the silicon-based SBD increases from 35ns to 38ns, with a variation rate of 8.6%; the SiC-based SBD increases from 8ns to 8.5ns, with a variation rate of 6.25%; the GaN-based SBD increases from 2ns to 2.1ns, with a variation rate of only 5%. All variations are within the industry-allowed safety threshold of ±10%. The slight increase in trr after aging is mainly due to the thermal aging of the metal-semiconductor barrier layer and the slight oxidation of the electrode contact surface, which increases the interface resistance and slows down the carrier drift speed, belonging to normal device aging phenomena with no significant impact on actual high-frequency application performance.
Process Details Affecting Reverse Recovery Time
The reverse recovery time of Schottky diodes is fundamentally determined by the metal-semiconductor barrier preparation process and semiconductor substrate manufacturing technology. Process deviations in metal electrode sputtering, substrate doping, junction area shaping, and packaging during mass production will directly lead to an increase in trr or poor batch consistency. The influence rules of each key process are as follows: First, metal-semiconductor barrier layer preparation. The barrier metal of silicon-based SBDs is usually titanium or platinum, with a sputtering thickness controlled at 50nm±5nm. A thickness deviation of ±10nm will cause the barrier height to fluctuate by ±0.05eV, leading to a trr variation of ±5ns. For SiC-based SBDs, nickel is used as the barrier metal, and the annealing temperature after sputtering is controlled at 950℃±20℃; insufficient annealing temperature will lead to incomplete formation of the metal-semiconductor alloy, increasing the interface state density and extending trr by 2-3ns.
Second, semiconductor substrate doping concentration control. The N-type substrate doping concentration of silicon-based SBDs is controlled at 5×10¹⁸ cm⁻³, a deviation of ±5×10¹⁷ cm⁻³ will cause the depletion layer width to change, leading to a trr fluctuation of ±4ns. High doping concentration reduces the depletion layer width and accelerates carrier drift, thus shortening trr, but it will also reduce the device's reverse voltage withstand capability. The SiC substrate doping concentration is controlled at 1×10¹⁶ cm⁻³, which is much lower than that of silicon-based SBDs, balancing voltage withstand capability and switching speed.
Third, junction area and edge shaping process. The junction area of Schottky diodes is directly proportional to the forward current capacity, but an excessively large junction area will increase the parasitic capacitance and extend trr. For a 5A rated SBD, the junction area is controlled at 0.2cm²±0.01cm²; an increase of 0.05cm² will increase the junction capacitance by 20pF and extend trr by 8-10ns. The edge of the junction area adopts a beveled design with a bevel angle of 45°±5° to eliminate edge electric field concentration; a deviation of ±10° will lead to uneven carrier distribution at the edge, increasing trr by 3-4ns and reducing the reverse voltage withstand capability.
Fourth, packaging and parasitic parameter control. The packaging parasitic inductance and capacitance of Schottky diodes have a significant impact on high-frequency switching performance. For SMA package SBDs, the parasitic inductance is controlled at ≤3nH and the parasitic capacitance at ≤5pF. Excessive parasitic inductance will cause voltage spikes during reverse recovery, distorting the current waveform and leading to inaccurate trr measurements; excessive parasitic capacitance will extend the charging and discharging time of the diode junction, increasing trr by 2-3ns. The lead bonding wire diameter is controlled at 0.2mm, and the bonding resistance is ≤1mΩ to avoid contact resistance affecting carrier transport speed.
Current Status of Commercial Application
From the perspective of industrial commercialization, silicon-based Schottky diodes, with their mature manufacturing processes, low production costs, and moderate switching performance, have achieved large-scale global commercialization, accounting for approximately 70% of the Schottky diode market share. They are mainly used in medium-frequency (≤1MHz) low-voltage rectification scenarios such as smartphone chargers, laptop power adapters, and low-power SMPS, with a rated current range of 1A-20A and a reverse voltage withstand range of 20V-200V, and a reverse recovery time of 20-50ns, balancing cost and performance requirements.
SiC-based Schottky diodes, with their ultra-short reverse recovery time and excellent high-temperature performance, have achieved large-scale commercialization, accounting for about 20% of the market share. They are mainly used in high-frequency (1MHz-10MHz) high-power scenarios such as new energy vehicle on-board chargers, industrial high-frequency inverters, and photovoltaic grid-connected converters, with a rated current range of 5A-50A and a reverse voltage withstand range of 600V-1200V, and a reverse recovery time of 5-10ns, which can improve circuit conversion efficiency by 3-5%. The production cost of SiC-based SBDs is 3-4 times that of silicon-based SBDs.
GaN-based Schottky diodes are currently in the stage of large-scale commercialization, accounting for about 8% of the market share. They are mainly used in ultra-high-frequency (≥10MHz) high-efficiency scenarios such as 5G base station power supplies, radar transmitter power modules, and aerospace electronic equipment, with a rated current range of 1A-10A and a reverse voltage withstand range of 100V-600V, and a reverse recovery time of ≤3ns, which is the best choice for ultra-high-frequency rectification. The production cost of GaN-based SBDs is 5-6 times that of silicon-based SBDs due to the high cost of GaN wafers and complex manufacturing processes.
In addition, aluminum nitride (AlN)-based Schottky diodes are currently in the small-batch production stage, accounting for about 2% of the market share. They have a reverse recovery time of ≤1ns and can work stably at 300℃ high temperature, showing excellent potential in extreme high-temperature and ultra-high-frequency application scenarios. However, the low yield rate of AlN wafers and high manufacturing costs restrict their large-scale popularization, and they are only used in a small number of high-end military and aerospace equipment.
Existing Technical Pain Points
1. Inherent contradiction between ultra-short reverse recovery time and high voltage withstand capability: The reverse recovery time of Schottky diodes is negatively correlated with the reverse voltage withstand capability. To achieve ultra-short trr, it is necessary to reduce the semiconductor substrate doping concentration and thin the depletion layer, which will lead to a significant reduction in the reverse voltage withstand capability. For example, a GaN-based SBD with trr = 2ns has a maximum reverse voltage withstand of only 600V, while a silicon-based SBD with a reverse voltage withstand of 200V has a trr of 35ns. The industry's heterojunction structure technology can balance the two indicators to a certain extent, but the voltage withstand capability can only be increased by about 20% under the premise of maintaining the same trr, which cannot meet the demand for high-voltage and ultra-fast switching in new energy vehicle high-voltage systems.
2. High-frequency parasitic parameter interference problem: At ultra-high frequencies above 10MHz, the packaging parasitic inductance and capacitance of Schottky diodes become the main factors limiting the switching speed, even if the intrinsic trr of the device is extremely short. For example, a GaN-based SBD with intrinsic trr = 2ns will have an actual measured trr of 5ns due to the influence of packaging parasitic parameters at 20MHz, which significantly reduces the high-frequency performance. Current advanced packaging technologies such as flip-chip bonding and wafer-level packaging can reduce parasitic parameters by 50%, but the production cost is increased by 2-3 times, making it difficult to popularize in mid-to-low-end application scenarios.
3. Batch consistency control difficulties: The reverse recovery time deviation of the same batch of Schottky diodes is a core process pain point in mass production. The trr deviation of silicon-based SBDs can reach ±5ns, SiC-based SBDs ±1ns, and GaN-based SBDs ±0.5ns. The core reasons are fluctuations in metal-semiconductor barrier thickness, substrate doping concentration deviations, and junction area shaping errors. Excessive deviation will lead to inconsistent switching speeds of devices in parallel applications, causing current imbalance and local overheating. To improve consistency, it is necessary to add high-frequency dynamic parameter sorting links, which directly reduce production efficiency and increase production costs by about 20%, making it difficult for small and medium-sized manufacturers to implement.
4. High-temperature reliability challenge of wide bandgap SBDs: Although SiC and GaN-based SBDs have excellent high-temperature performance, at temperatures above 200℃, the metal-semiconductor barrier layer will undergo thermal degradation, leading to an increase in trr and a decrease in forward voltage drop. For example, a SiC-based SBD with trr = 8ns at 25℃ will have a trr of 12ns at 250℃, with a variation rate of 50%. Current barrier layer passivation technologies can improve high-temperature stability by 30%, but cannot fundamentally solve the thermal degradation problem of the metal-semiconductor interface, which restricts the application of wide bandgap SBDs in extreme high-temperature scenarios such as aerospace engine control systems.
5. Cost-performance balance constraints: High-performance SiC and GaN-based Schottky diodes have ultra-short reverse recovery time and high efficiency but high production costs, which cannot be popularized in low-cost consumer electronics scenarios; low-cost silicon-based SBDs have relatively long trr and cannot meet the high-frequency and high-efficiency requirements of new energy and 5G industries. There is no Schottky diode in the industry that can balance ultra-short reverse recovery time, high voltage withstand capability, high-temperature stability, and low cost, so different scenarios can only select models according to needs, forming a trade-off between performance and cost.